1. Field of the Invention
The present invention relates to an electrically erasable programmable logic device (EEPLD) for use as non-volatile memory. More particularly, the present invention relates to an electrically erasable programmable read only memory device capable of implementing multi-level program operations. According to the present invention, the electrically erasable programmable read only memory is compatible with standard CMOS manufacturing processes and the dimension of the electrically erasable programmable read only memory unit is shrunk.
2. Description of the Prior Art
With demands for portable electrical products in recent years, techniques of electrically erasable programmable read-only memory (EEPROM) have been matured and the market has expanded. EEPROM could be applied in digital cameras, video game consoles, personal digital assistants, recording devices of telephones, and programmable IC products. EEPROM is a non-volatile memory, which changes threshold voltage of transistors or memory cells to control open and close of a corresponding gate channel to store memory data instead of lose because of power shutdown.
Single-poly electrically erasable programmable read only memory (EEPROM) device is known in the art. FIG. 1 shows a conventional single-poly electrically erasable programmable read only memory device, which was disclosed in “A single-poly EPROM for custom CMOS logic applications”, IEEE Custom Integrated Circuits Conference, p.59-62, 1986, by R. Kazerounian et al. As shown in FIG. 1, the prior art single-poly EPROM 10 is formed on a substrate 12. A large area N-well 14 functioning as a coupling gate with respect to a floating gate 16 is provided. Through the coupling well 14, a high-level voltage such as a voltage of 9V to 12V is capacitively coupled to the floating gate 16, thereby generating channel hot electrons in the substrate 12 under the floating gate 16. The channel hot electrons inject into the floating gate 16 and change the threshold voltage of the floating gate to store binary data such as “0” or “1”. Because the single-poly structure is simple, it could be generated in standard CMOS layout processing instead of costly multi-gate technique.
However, one disadvantage of the above-described prior art single-poly EPROM 10 is that its large-area coupling gate, i.e., N-well 14, consumes a lot of valuable chip area. The N-well 14 with a relative big measure has to be applied to couple high potential voltage to the floating gate 16. The measure of the N-well 14 is larger than other parts of the memory cell, which prevents the memory area size applied with the single-poly memory cell 10 from reduction.